1. Field of the Invention
The present invention relates to a sense amplifier used, for example, in a signal input circuit or a memory read-out circuit, and to a semiconductor integrated circuit applied, for example, to an address transition detector for detecting a change of a memory address signal.
2. Description of the Related Art
FIG. 24 shows a conventional input circuit. The input circuit comprises a comparator 10 and an output circuit OB constituted by CMOS inverter circuits. (hereinafter, called "CMOS output circuit").
The comparator 10 is constituted by a differential amplifier. Specifically, an input voltage Vin is supplied to the gate of a P-channel transistor 11 which is an element of the comparator 10. A reference voltage Vref is supplied to the gate of a P-channel transistor 12. The sources of the transistors 11 and 12 are connected to a power source V.sub.DD via a P-channel transistor 13 which constitutes a current source. The drains of the transistors 11 and 12 are connected to the drains of N-channel transistors 14 and 15. The gates of the N-channel transistors 14 and 15 are commonly connected to the drain of the N-channel transistor 14. The sources of the transistors 14 and 15 are grounded. The connection node between the drain of the N-channel transistor 15 and the drain of the P-channel transistor 12 is connected in series to inverter circuits 16 and 17 which constitute the output circuit OB.
On the other hand, the gate of the P-channel transistor 13, which constitutes the current source, is connected to the gate of a P-channel transistor 18. The source of the P-channel transistor 18 is connected to a power source V.sub.DD, and the drain of the transistor 18 is connected to the gate of the transistor 18. The drain of the transistor 18 is also connected to the drain of an N-channel transistor 20 via a resistor 19. The source of the transistor 20 is grounded, and the gate thereof is connected to a constant bias source (not shown).
With the above structure, if a voltage equal to a threshold value of the input circuit is supplied as reference voltage Vref, the operation with the accurate threshold value can be performed.
Regarding the input circuit with the above structure, if threshold values VthP and VthN of the P-channel transistors and N-channel transistors are varied owing to a variance in the semiconductor manufacturing process, a response time tpLH in the case where the input voltage Vin changes from a high level to a low level is varied. In addition, a response time tpHL in the case where the input voltage Vin changes from the low level to the high level is varied, and the difference therebetween, .DELTA.tp=.vertline.pLH-tpHL.vertline., increases.
FIGS. 25A to 25C are views for explaining the operation of the input circuit shown in FIG. 24. As is shown in FIG. 25A, when the input voltage Vin changes from the high level to the low level or from the low level to the high level, the output voltage Vc of the comparator 10 varies, as shown in FIG. 25B. When the threshold value Vthc of the inverter circuit 16, which constitutes the output circuit, becomes higher than an operation point A of the comparator 10 owing to a variance in the manufacturing process, the output voltage Vout of the inverter circuit 17 varies, as shown in FIG. 25C. In other words, the response times tpHL and tpLH increase, and also the difference Atp therebetween increases.
FIGS. 26 and 27 show results of simulation of the input circuit shown in FIG. 25, which results were obtained by use of a well-known SPICE (a circuit simulator developed by University of California). Specifically, output signals in relation to input voltages are shown. The conditions for the simulation are: the channel length of each transistor is longer than a standard length, e.g. by 0.2 .mu.m; the threshold value VthP of the P-channel transistor is lower than a standard length, e.g. by 0.25 V; and the threshold value VthN of the N-channel transistor is higher than a standard length, e.g. by 0.25 V. The voltage of the power source V.sub.DD is 4.75 V.
As is shown in FIG. 26, the response time tpLH of the output signal Vo in relation to the rising of the input voltage Vin is 3.8 ns, and, as shown in FIG. 27, the response time tpLH of the output signal Vo in relation to the falling of the input voltage Vin is 1.8 ns. The difference between the response times is EQU .vertline.tpLH-tpHL=2.6 ns
On possible means for decreasing the response times tpHL and tpLH is to make steeper the inclination of the output voltage of the comparator 10, which is shown in FIG. 25B. In this case, however, it is necessary to make the current value of the current source excessively higher, and this is practically impossible.